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1 ? fn2867.9 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002, 2004, 2005, 2006. all rights reserved all other trademarks mentioned are the property of their respective owners. icm7555, icm7556 general purpose timers the icm7555 and icm7556 are cmos rc timers providing significantly improved performance over the standard se/ne 555/6 and 355 timers, while at the same time being direct replacements for those devices in most applications. improved parameters inclu de low supply current, wide operating supply voltage range, low threshold, trigger and reset currents, no crowbarring of the supply current during output transitions, higher frequency performance and no requirement to decouple control voltage for stable operation. specifically, the icm7555 and icm7556 are stable controllers capable of producing accurate time delays or frequencies. the icm7556 is a dual icm7555, with the two timers operating independently of each other, sharing only v+ and gnd. in the one shot mode, the pulse width of each circuit is precisely controlled by one external resistor and capacitor. for astable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled by two external resistors and one capacitor. unlike the regular bipolar se/ne 555/6 devices, the control voltage terminal need not be decoupled with a capacitor. the circuits are triggered and reset on falling (negative) waveforms, and the output inverter can source or sink currents large enough to drive ttl loads, or provide minimal offsets to drive cmos loads. features ? exact equivalent in most cases for se/ne555/556 or tlc555/556 ? low supply current - icm7555 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 a - icm7556 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 a ? extremely low input currents . . . . . . . . . . . . . . . . . 20pa ? high speed operation . . . . . . . . . . . . . . . . . . . . . . . 1mhz ? guaranteed supply voltage range . . . . . . . . . 2v to 18v ? temperature stability . . . . . . . . . . . . 0.005%/c at +25c ? normal reset function - no crowbarring of supply during output transition ? can be used with higher impedance timing elements than regular 555/6 for longer rc time constants ? timing from microseconds through hours ? operates in both astable and monostable modes ? adjustable duty cycle ? high output source/sink driver can drive ttl/cmos ? outputs have very low offsets, hi and lo ? pb-free plus anneal available (rohs compliant) applications ? precision timing ? pulse generation ? sequential timing ? time delay generation ? pulse width modulation ? pulse position modulation ? missing pulse detector pinouts icm7555 (8 ld pdip, soic) top view icm7556 (14 ld pdip, cerdip) top view gnd trigger output reset 1 2 3 4 8 7 6 5 v dd discharge threshold control voltage discharge thresh- control reset output trigger gnd v dd discharge threshold control reset output trigger 1 2 3 4 5 6 7 14 13 12 11 10 9 8 voltage voltage old data sheet august 24, 2006
2 fn2867.9 august 24, 2006 ordering information part number part marking temp. range (c) package pkg. dwg. # icm7555cba 7555 cba 0 to +70 8 ld soic m8.15 icm7555cba-t 7555 cba 0 to +70 8 ld soic tape and reel m8.15 icm7555cbaz (note) 7555 cbaz 0 to +70 8 ld soic (pb-free) m8.15 ICM7555CBAZ-T (note) 7555 cbaz 0 to +70 8 ld soic (pb-free) tape and reel m8.15 icm7555iba 7555 iba -25 to +85 8 ld soic m8.15 icm7555ibat 7555 iba -25 to +85 8 ld soic tape and reel m8.15 icm7555ibaz (note) 7555 ibaz -25 to +85 8 ld soic (pb-free) m8.15 icm7555ibaz-t (note) 7555 ibaz -25 to +85 8 ld soic (pb-free) tape and reel m8.15 icm7555ipa 7555 ipa -25 to +85 8 ld pdip e8.3 icm7555ipaz (note) 7555 ipaz -25 to +85 8 ld pdip** (pb-free) e8.3 icm7556ipd icm7556ipd -25 to +85 14 ld pdip e14.3 icm7556ipdz (note) icm7556ipdz -25 to +85 14 ld pdip** (pb-free) e14.3 icm7556mjd icm7556mjd -55 to +125 14 ld cerdip f14.3 **pb-free pdips can be used for through hole wave solder processi ng only. they are not intended for use in reflow solder proces sing applications. note: intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. icm7555, icm7556
3 fn2867.9 august 24, 2006 absolute maximum rati ngs thermal information supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+18v input voltage trigger , control voltage, threshold, reset (note 1) . . . . . . . . . . . . . . . . . . . . . v+ +0.3v to gnd -0.3v output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ma operating conditions temperature range icm7555c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c icm7555i, icm7556i . . . . . . . . . . . . . . . . . . . . . . -25c to +85c icm7556m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c thermal resistance (typical, note 2) ja (c/w) jc (c/w) 14 lead cerdip package. . . . . . . . . . 80 24 14 lead pdip package* . . . . . . . . . . . 115 n/a 8 lead pdip package* . . . . . . . . . . . . 130 n/a 8 lead soic package . . . . . . . . . . . . . 170 n/a maximum junction temperature (hermetic package) . . . . . . . +175c maximum junction temperature (plastic package) . . . . . . . +150c maximum storage temperature range . . . . . . . . -65c to +150c maximum lead temperature (soldering 10s) . . . . . . . . . . . +300c (soic - lead tips only) * pb-free pdips can be used for through hole wave solder processing only. they are not intended for use in reflow solder processing applications. caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. due to the scr structure inherent in the cmos process used to fabricate these devices , connecting any terminal to a voltage g reater than v+ +0.3v or less than v- -0.3v may cause destructive latchup. for this reason it is recommended that no inputs from external sour ces not operating from the same power supply be applied to the device befor e its power supply is establish ed. in multiple supply system s, the supply of the icm7555 and icm7556 must be turned on first. 2. ja is measured with the component mounted on a low effective therma l conductivity test board in free air. see tech brief 379 for details. electrical specifications applies to icm7555 and icm7556, unless otherwise specified parameter symbol test conditions t a = +25c (note 4) -55c to + 125c units min typ max min typ max static supply current i dd icm7555 v dd = 5v 40 200 300 a v dd = 15v 60 300 300 a icm7556 v dd = 5v 80 400 600 a v dd = 15v 120 600 600 a monostable timing accuracy r a = 10k, c = 0.1 f, v dd = 5v 2 % 858 1161 s drift with temperature (note 3) v dd = 5v 150 ppm/ c v dd = 10v 200 ppm/ c v dd = 15v 250 ppm/ c drift with supply (note 3) v dd = 5v to 15v 0.5 0.5 %/v astable timing accuracy r a = r b = 10k, c = 0.1 f, v dd = 5v 2 % 1717 2323 s drift with temperature (note 3) v dd = 5v 150 ppm/ c v dd = 10v 200 ppm/ c v dd = 15v 250 ppm/ c drift with supply (note 3) v dd = 5v to 15v 0.5 0.5 %/v threshold voltage v th v dd = 15v 62677161 72% v dd trigger voltage v trig v dd = 15v 28323627 37% v dd trigger current i trig v dd = 15v 10 50 na threshold current i th v dd = 15v 10 50 na control voltage v cv v dd = 15v 62677161 72% v dd icm7555, icm7556
4 fn2867.9 august 24, 2006 functional diagram reset voltage v rst v dd = 2v to 15v 0.4 1.0 0.2 1.2 v reset current i rst v dd = 15v 10 50 na discharge leakage i dis v dd = 15v 10 50 na output voltage v ol v dd = 15v, i sink = 20ma 0.4 1.0 1.25 v v dd = 5v, i sink = 3.2ma 0.2 0.4 0.5 v v oh v dd = 15v, i source = 0.8ma 14.3 14.6 14.2 v v dd = 5v, i source = 0.8ma 4.0 4.3 3.8 v discharge output voltage v dis v dd = 5v, i sink = 15ma 0.2 0.4 0.6 v v dd = 15v, i sink = 15ma 0.4 v supply voltage (note 3) v dd functional operation 2.0 18.0 3.0 16.0 v output rise time (note 3) t r r l = 10m, c l = 10pf, v dd = 5v 75 ns output fall time (note 3) t f r l = 10m, c l = 10pf, v dd = 5v 75 ns oscillator frequency (note 3) f max v dd = 5v, r a = 470 , r b = 270 , c = 200pf 1mhz notes: 3. these parameters are based upon characterization data and are not tested. 4. applies only to military temperature range product (m suffix). electrical specifications applies to icm7555 and icm7556, unless otherwise specified (continued) parameter symbol test conditions t a = +25c (note 4) -55c to + 125c units min typ max min typ max + - threshold control voltage 6 5 3 1 + - trigger 2 comparator r gnd b comparator a r v dd 8 output 7 1 n discharge output drivers flip-flop reset 4 r note: this functional diagram reduces the circuitry down to its simplest equivalent components. tie down unused inputs. truth table threshold voltage trigger voltage reset output discharge switch don?t care don?t care low low on > 2 / 3 (v+) > 1 / 3 (v+) high low on < 2 / 3 (v+) > 1 / 3 (v+) high stable stable don?t care < 1 / 3 (v+) high high off note: reset will dominate all other inputs: trigger will dominate over threshold. icm7555, icm7556
5 fn2867.9 august 24, 2006 schematic diagram application information general the icm7555 and icm7556 devices are, in most instances, direct replacements for the ne/se 555/6 devices. however, it is possible to effect eco nomies in the external component count using the icm7555 and icm7556. because the bipolar ne/se 555/6 devices produce large crowbar currents in the output driver, it is necessary to decouple the power supply lines with a good capacitor close to the device. the icm7555 and icm7556 devices produce no such transients. see figure 1. the icm7555 and icm7556 produce supply current spikes of only 2ma - 3ma instead of 300ma - 400ma and supply decoupling is normally not necessary. also, in most instances, the control voltage decoupling capacitors are not required since the in put impedance of the cmos comparators on chip are very high. thus, for many applications, two capacitors can be saved using an icm7555 and three capacitors with an icm7556. power supply considerations although the supply current consumed by the icm7555 and icm7556 devices is very low, the total system supply current can be high unless the timing components are high impedance. therefore, use high values for r and low values for c in figures 2a, 2b, and 3. reset discharge trigger threshold gnd output control voltage r nn npn p r r v dd n n n n n p p n n p p p r = 100k 20% (typ) time (ns) 400 800 600 200 0 0 100 200 300 400 500 supply current (ma) se/ne555 t a = 25c icm7555/56 figure 1. supply current transient compared with a standard bipolar 555 during an output transition gnd trigger output reset 1 2 3 4 8 7 6 5 v dd discharge threshold control voltage v dd 10k alternate output optional capacitor c v dd r figure 2a. astable operation icm7555, icm7556
6 fn2867.9 august 24, 2006 output drive capability the output driver consists of a cmos inverter capable of driving most logic families including cmos and ttl. as such, if driving cmos, the output swing at all supply voltages will equal the supply voltage. at a supply voltage of 4.5v or more, the icm7555 and icm7556 will drive at least two standard ttl loads. astable operation the circuit can be connected to trigger itself and free run as a multivibrator, see figure 2a. the output swings from rail to rail, and is a true 50% duty cycl e square wave. (trip points and output swings are sym metrical.) less than a 1% frequency variation is observed over a voltage range of +5v to +15v. the timer can also be connected as shown in figure 2b. in this circuit, the frequency is: the duty cycle is controll ed by the values of r a and r b , by the equation: monostable operation in this mode of operation, th e timer functions as a one-shot. see figure 3. initially the external capacitor (c) is held discharged by a transistor inside the timer. upon application of a negative trigger pulse to pin 2, the internal flip-flop is set which releases the short circuit across the external capacitor and drives the output high. the voltage across the capacitor now increases exponentially with a time constant t = r a c. when the voltage across the capacitor equals 2 / 3 v+, the comparator resets the flip-flop, which in turn discharges the capacitor rapidly and also drives the output to its low state. trigger must return to a high state before the output can return to a low state. control voltage the control voltage terminal permits the two trip voltages for the threshold and trigger internal comparators to be controlled. this provides the possibility of oscillation frequency modulation in the astable mode or even inhibition of oscillation, depending on the applied voltage. in the monostable mode, delay times can be changed by varying the applied voltage to the control voltage pin. reset the reset terminal is designed to have essentially the same trip voltage as the standar d bipolar 555/6, i.e., 0.6v to 0.7v. at all supply voltages it represents an extremely high input impedance. the mode of operation of the reset function is, however, much improved over the standard bipolar ne/se 555/6 in that it c ontrols only the internal flip- flop, which in turn controls simultaneously the state of the output and discharg e pins. this avoids the multiple threshold problems sometimes encountered with slow falling edges in the bipolar devices. output 1 2 3 4 8 7 6 5 v dd optional capacitor c v dd r a r b figure 2b. alternate astable configuration f 1 1.4 rc ------------------ = (eq. 1) f1.44r a 2r b + () ? c = (eq. 2) dr a r b + () r a 2r b + () ? = (eq. 3) trigger output reset 1 2 3 4 8 7 6 5 v dd discharge threshold control voltage optional capacitor c v dd 18v r a icm7555 t output = -ln (1/3) r a c = 1.1r a c figure 3. monostable operation icm7555, icm7556
7 fn2867.9 august 24, 2006 typical performance curves figure 4. minimum pulse width required for triggering figure 5. supply current vs supply voltage figure 6. output source current vs output voltag e figure 7. output sink current vs output voltage figure 8. output sink current vs output voltag e figure 9. output sink current vs output voltage t a = 25c v dd = 2v v dd = 18v lowest voltage level of trigger pulse (%v dd ) v dd = 5v minimum pulse width (ns) 010203040 0 1200 1100 1000 900 800 700 600 500 400 300 200 100 supply voltage (v) t a = 25c supply current (icm7555) ( a) supply current (icm7556) ( a) t a = -20c t a = 70c 0 2 4 6 8 10121416 18 20 0 200 180 160 140 120 100 80 60 40 20 400 360 320 280 240 200 160 120 80 40 0 t a = 25c v dd = 2v v dd = 5v v dd = 18v output source current (ma) -100 -10.0 -1.0 -0.1 -0.01 -0.1 -1.0 -10 output voltage referenced to v dd (v) t a = -20c output low voltage (v) v dd = 2v v dd = 5v v dd = 18v output sink current (ma) 0.01 0.1 1.0 10.0 0.1 100 10.0 1.0 t a = 25c output low voltage (v) v dd = 2v v dd = 5v v dd = 18v output sink current (ma) 0.01 0.1 1.0 10.0 0.1 100 10.0 1.0 t a = 70c output low voltage (v) v dd = 2v v dd = 5v v dd = 18v output sink current (ma) 0.01 0.1 1.0 10.0 0.1 100 10.0 1.0 icm7555, icm7556
8 fn2867.9 august 24, 2006 figure 10. normalized frequency stability in the astable mode vs supply voltage figure 11. discharge output current vs discharge output voltage figure 12. propagation delay vs voltage level of trigger pulse figure 13. normalized frequency stability in the astable mode vs temperature figure 14. free running frequency vs r a , r b and c figure 15. time delay in the monostable mode vs r a and c typical performance curves (continued) supply voltage (v) t a = 25c normalized frequency deviation (%) r a = r b = 10m 0.1 1.0 10.0 100.0 8 8 6 4 2 0 2 4 6 c = 100pf r a = r b = 10k c = 0.1 f t a = 25c discharge low voltage (v) v dd = 2v v dd = 5v v dd = 18v discharge sink current (ma) 0.01 0.1 1.0 10.0 0.1 100 10.0 1.0 t a = 25c lowest voltage level of trigger pulse (%v dd ) v dd = 5v propagation delay (ns) 010203040 0 600 500 400 300 200 100 t a = 70c t a = -20c temperature (c) normalized frequency deviation (%) 06080 -0.1 +0.1 0 r a = r b = 10k c = 0.1 f 40 20 -20 +0.2 +0.3 +0.4 +0.5 +0.6 +0.7 +0.8 +0.9 +1.0 v dd = 2v v dd = 5v v dd = 18v v dd = 2v t a = 25c frequency (hz) (r a + 2r b ) 1k 10k 100k 1m 10m 100m 10 0.1 1 100 1k 10k 100k 1m 10m capacitance (f) 1.0 100m 10m 1m 100 10 1 100n 10n 1n 100p 10p 1p time delay (s) 1k 10k 100k 1m 10m 100m 10 100n 1 100 1m 10m 100m 1 10 capacitance (f) 1.0 100m 10m 1m 100 10 1 100n 10n 1n 100p 10p 1p r a t a = 25c icm7555, icm7556
9 fn2867.9 august 24, 2006 icm7555, icm7556 small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 8 0 8 - rev. 1 6/05
10 fn2867.9 august 24, 2006 icm7555, icm7556 dual-in-line plastic packages (pdip) c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a 1 -a- 0.010 (0.25) c a m bs notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo se ries symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protru- sions. mold flash or protrusi ons shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e8.3 (jedec ms-001-ba issue d) 8 lead dual-in-line plastic package symbol inches millimeters notes min max min max a- 0.210 - 5.33 4 a1 0.015 - 0.39 -4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.355 0.400 9.01 10.16 5 d1 0.005 - 0.13 -5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n8 89 rev. 0 12/93
11 fn2867.9 august 24, 2006 icm7555, icm7556 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpen- dicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not incl ude dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e14.3 (jedec ms-001-aa issue d) 14 lead dual-in-line plastic package symbol inches millimeters notes min max min max a- 0.210 - 5.33 4 a1 0.015 - 0.39 -4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 -5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n14 149 rev. 0 12/93
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn2867.9 august 24, 2006 icm7555, icm7556 ceramic dual-in-line fr it seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this c onfiguration dimension b3 replaces dimension b2. 5. this dimension allows for off- center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f14.3 mil-std-1835 gdip1-t14 (d-1, configuration a) 14 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a- 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d- 0.785 - 19.94 5 e 0.220 0.310 5.59 7.87 5 e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 -7 90 105 90 105 - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m- 0.0015 - 0.038 2, 3 n14 148 rev. 0 4/94

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